Electrical power inverters typically utilize pairs of semiconductor switches that are connected together across DC bus or supply lines to which a DC voltage source is connected. The switches are alternately turned on and off in a selected switching sequence to provide AC power to a load connected to a node between the two switches. The high side semiconductor switches are almost always selected to be n-type devices because of their superior switching characteristics and low on-resistance compared to p-type devices. As a result, the high side switch requires a floating voltage source and level-shift function that contributes to the cost and complexity of the inverter gate drive. A single pair of semiconductor switches connected in this manner may be used by itself to provide single phase AC power to a load, or two pairs of switches may be connected together in a conventional H-bridge configuration, for single phase power, three pairs of switches for three phase power, and so on. Each pair of switches may be considered a phase leg of a single phase or multiphase inverter.
Because the two switches of the phase leg are connected in series across the DC bus lines, if both of the switches are turned on simultaneously a potentially catastrophic shoot-through condition exists in which short circuit current through the switches could burn out the switches or damage other circuit components. In conventional phase leg configurations, dead time is almost always added to the gate drive signals provided to the switches to ensure that one of the switches is completely turned off before the other switch is turned on. However, the presence of dead time can add a significant amount of undesired non-linearity and harmonic distortion to the pulse width modulated (PWM) output voltage waveforms. Depending on the current direction, the actual phase voltage can gain or lose voltage in comparison to the ideal PWM waveform. The output waveform distortion and the voltage amplitude loss of the fundamental-frequency component become worse as either the fundamental frequency or the carrier frequency increases.
Many different methods for compensating for dead time have been proposed, typically by compensating the effects of dead time indirectly using appropriate control methods to modify the PWM commands. Measured phase current polarity information is often required to carry out these compensation algorithms. The very fast (sub-microsecond) time scale for phase leg switching, combined with practical difficulties associated with zero-crossing detection errors, has made it difficult to satisfactorily achieve dead time compensation under all conditions, and the added complexity of such approaches also increases the total cost of the inverter.
Various circuits have been proposed for preventing shoot-through by effectively sensing current flow through the switches and ensuring the turn-off of a conducting switch before the other is turned on. See U.S. Pat. Nos. 4,126,819, 5,646,837 and 5,859,519 and published U.S. patent application US2001/0048278A1. Such circuits require significant additional components, with significant added cost, or still require delays between turn-off and turn-on of the switches with corresponding dead time in the PWM waveforms.